IPC 4761 Via Plugging Guideline
IPC-4761 - Summary of Specification
IPC-4761 reflects IPC's work towards standardizing the via plugging process. To summarize, this document classifies 7 different types of via plugs. Two of these are dedicated to the use of dry film soldermask, which now has only limited usage and applications. From what we know, this usage is primarily limited to older military applications. The remainder, we would separate between via plugging and Via-in-Pad as these two types of via plugs serve very different purposes.
Historically, and even continuing to today, the requirement for via plugging in designs has simply been called out as "via must be plugged", with some diligent designers calling out that they must be plugged with an epoxy. Overall, this is a very ambiguous callouts that IPC-4761 serves to lend discipline and clarity to.
Since we are a provider of commercial printed circuit boards, we most often encounter the middle grouping of via plug types (III, IV, V, & VI), which we be the focus of this article. Reviewing the IPC 4761 document from Type III through Type VI, I can't help but think that this is somewhat of a dangerous document. Based on my experience in plugging vias, I would say that types III and IV are nothing but an incremental step on the way to achieving a Type V or VI via.
Now, it's very easy to look at a cartoon picture and say "That's what I want!" and include that in your fabrication notes. It's whole other story when you actually have to achieve in real life what the nice cartoon depicts. With larger via sizes (0.016" and up) in a 0.062" typical thickness PCB, achieving a Type V or VI via plug is not too difficult--though still time consuming. However, trying to screen a low shrinkage ink into a 0.012" via (and often down to 0.008") and fill it entirely is a much more difficult target to hit.
Given the difficulties in achieving a Type VI(b) via fill, IPC should almost create a Type VI(c), which depicts the attempt at a Type VI in which the plugging ink only fills a portion of the via, and the rest of it is filled with soldermask. While this may not be technically correct, I would wager that this is what most actual boards look like given the difficulty in achieving a full plug.
Assuming that my statement is correct in that typical Type VI via fills come out as per the above depiction, it would be worthwhile for IPC to generate tests of this outcome for long-term reliability.
Via Plugging Process Description
The primary challenge is trying to force the required volume of ink into that small of a hole. To get a better understanding of the challenge, it is important to understand the process by which the ink is applied. The first step is to create a screen through which the plugging ink is passed into the hole. The screen is prepared by applying an emulsion over the entire working area. This emulsion is a photoimageable ink that reacts to UV light. We then image the emulsion with a dot pattern that replicates the locations of the vias to be plugged. Once imaged and developed, the emulsion will remain in all areas in which plugging ink is not required. The areas over the vias will be free of emulsion ink, allowing a path through which the ink can travel through the screen and into the vias.
The total thickness of the screen is typically 0.004". Including the emulsion, the total may be approximately 0.006". Each stroke of the squeegee will theoretically push this thickness of plugging ink into the hole. Therefore, if this assumption holds true, then a minimum of 10 strokes will be required to fill a hole in a panel thickness of 0.062". In practice, we have seen smaller vias holes (e.g., 0.012" and smaller) require up to 20 strokes and even with this we have found that not all vias are fully plugged.
In summary, requiring a Type V or VI fully plugged via can add significant cost to cover both labor & machine time, as well as fallout at both the fabricator and end user should the PCBs be rejected for not achieving a full plug.
This begs the question, "Why do I need a fully plugged via?"
Concerns Over Type III & IV Via Plugs
The IPC-4761 document takes the opportunity to explain why one should be concerned over each time of via plug. They do also make a note on Type V and VI via plugs in that there should be a concern in the complexity of obtaining a complete fill. There must have been a PCB fabricator on the committee who spoke up.
However, I'll take this opportunity to address the concerns listed over solely the Type III & IV via plugs and attempt to alleviate those. Important note: I will focus on the effect of the concern in the end, deliverable product.
Concern 1: Via plug should not be used with bare copper hole walls
Why not? This is one of the fundamental issues I have with certain specifications. It would be ideal to know why or why isn't a particular feature good for a PCB. Other times it would be great to know what testing or test results lead to a particular specification. In this case, I would argue that a via that is plugged only from one side would result in the exposed copper being coated with the final finish. Often, if this particular feature type isn't compatible with a final finish, it will result in other rejectable anomalies such as exposed copper on the surface due to skip plating.
In the cases where the plug is from both sides and you have exposed copper in the barrel, the concern is, understandably, oxidation of the plated hole wall resulting in a latent failure. My experience so far is that surface copper is covered with either soldermask or a plating to keep the copper from being exposed to air. In the case of a 2-sided plug, there would be air in the via, but it would be stagnant. My question to the IPC board would be "Is there a diminished impact of the air trapped in the via as opposed to constantly replenished air against copper?". I think it would be great if they came up with a test for this. One idea would be to create a daisy chain coupon with a 2-sided plug and measure the resistance at start. Then you could either thermal cycle or keep at high temperature / high humidity and measure at 250-hour increments. Any vias that cause a change in values can then be cross sectioned to determine if the root cause of failure was oxidation of the hole wall.
Concern 2: Outgassing / Blow-Outs
Agreed. But this is a failure mode that the bare board would be rejected for. If the PCB has a HASL finish, then any outgassing concerns would be evident on the bare board as the thermal shock in this process is much greater than that incurred during PCB assembly. If it survives this process, then it should be considered rugged enough to last for the rest of the product's life cycle. Furthermore, if there is a conformal coating / potting process during final assembly, then concerns of exposed copper potentially do not apply. However, this may still be a concern for non-HASL finishes. In any event, this should be pointed out in the IPC document and not for the user to discern.
Concern 3: Removal of chemistries
The concern here is that the higher the aspect ratio, the more concern there should be of the removal of chemistries. Agreed. However, this is a bare board concern. Dragging chemistries from one bath to another in most immersion processes results in "skip plating", which manifests itself in exposed surface copper. This is a rejectable PCB characteristic and would never make to the finished product anyway. In the case of a HASL finish, the only chemistries the board should see after the plugging process should be RO Water, which is typically dried out in final washing. Again, it would be great to know exactly which chemistries are of concern so that PCB fabricators can work together with their customers to alleviate.
Summary
In summary, while I think this standard did a great job of explaining the differences between the types of available via plugging, I think it needs more work to really define to the end user when each type of plug should be allowable or not. Also, there should be cross qualifications (e.g., a type VI backward qualifies as meeting Type III or IV, etc.). If there's anyone out there willing to put together the testing methodology, I'm more than happy to build the test vehicles.
Yash Sutariya
Saturn Electronics Corporation
Saturn Flex Systems, Inc.